Vector Add
C[i] = A[i] + B[i]; representative PTX with illustrative timeline spans
Synthetic logical-pipeline timeline
Synthetic single-warp serial view; spans are relative model units, not measured cycles
Pipeline labels follow Nsight Compute logical categories. Final SASS dispatch is compiler-, instruction-, and target-dependent.
Sources: PTX ISA · Nsight pipeline taxonomy
Model unit 033 units
FMA
ALU
ADU
LSU
TMA
XU
Tensor
CBU
FMA
ALU
ADU
LSU
TMA
XU
Tensor
CBU
Instruction details for ld.global.f32 %f1, [%rd1];
LSU Pipeline
ld.global.f32 %f1, [%rd1];
Load A[i] through the memory pipeline
SASS family
LDG family
Model span
12 units
Logical category
LSU
Regs
%f1, %rd1
PTX → SASS boundary
SASS mnemonics are representative compiler output, not a one-to-one PTX mapping. NVIDIA does not publish a stable instruction bit layout; inspect the binary built for your target with cuobjdump or nvdisasm.
Register Usage
%f1%rd1
Pipeline Legend
FMA: Fused Multiply-Add
ALU: Integer & Logic
ADU: Address Divergence / Constant / CTA Barrier
LSU: Load / Store Unit
TMA: Tensor Memory Accelerator
XU: Special Function (SFU)
Tensor: Tensor Core (MMA)
CBU: Convergence Barrier